Referring to FIG. 1, a conventional quad flat no-lead (QFN) lead frame includes an outer frame 11, a metallic die pad 12 surrounded by the outer frame 11, a connecting portion 13 connected between the metallic die pad 12 and the outer frame 11, and a plurality of spaced-apart leads 14 extending from the outer frame 11 toward the metallic die pad 12 in a spaced-apart manner. Referring to FIG. 2, when the conventional QFN lead frame is packaged, a chip 100 is first disposed on the metallic die pad 12, and then a plurality of wires 15 are connected between the metallic die pad 12 and the spaced-apart leads 14. Finally, the chip 100 and the outer frame 11 are covered by a polymeric encapsulating material, followed by curing the polymeric encapsulating material to form a polymeric encapsulating layer 16, and a chip package device is obtained.
However, considering that the operability of the packing process and poor adhesion strength between the polymeric encapsulating layer 16 and the metallic die pad 12 may adversely affect reliability and performance of the chip package device, a ratio of an area of a surface of the chip 100 attached to the metallic die pad 12 to an area of a surface of the metallic die pad 12 for disposing the chip 100 is controlled to lie within a range of 0.6 to 0.8. By way of maintaining the abovementioned ratio, heterogeneous interfaces between the polymeric encapsulating layer 16 and the metallic die pad 12 can be reduced. Nevertheless, when the size of the chip 100 to be disposed on the conventional QFN lead frame is changed, it is necessary to produce a new conventional QFN lead frame with the metallic die pad 12 having a size that matches the size of the chip 100 for maintaining the abovementioned ratio.